1. Field of the Invention
The present invention relates to a semiconductor device applicable to an insulated gate type field effect transistor (MOSFET), a conductivity modulation type MOSFET (IGBT), a bipolar transistor, a diode, or the like, and a method of manufacturing the semiconductor device.
2. Description of the Related Art
More particularly, the invention relates to a DMOS for use in a semiconductor relay (SSR).
A conventional semiconductor device will be described by reference to FIGS. 1A, 1B, and 2. FIG. 1A is a longitudinal cross sectional diagram of a conventional vertical double-diffused MOS (vertical DMOS). Whereas, FIG. 1B is an electric field intensity distribution diagram at immediately before breakdown along the direction of thickness (longitudinal direction) within the device of FIG. 1A. Further, FIG. 2 is a layout diagram of the conventional example of FIG. 1A.
The conventional example of FIGS. 1A and 2 is composed of an n− drift layer 1 formed of an n type silicon, a p base layer 2, a p+ layer 3, an n+ layer 4, an n+ layer 5, an oxide film layer 6, a gate electrode 7, a source electrode 8, a drain electrode 9, a guard ring 10, an oxide film layer 12, a field plate 13, a gate pad 14, and a source pad 15.
Thus, D denotes the thickness of the device, and W denotes the width of the device. Then, the direction of the thickness D of the n− drift layer 1 is the longitudinal direction, and the direction of the width W of the device is the transverse direction. Incidentally, below, an element bearing a reference sign n in its name denotes the element using electrons as majority carriers, and an element bearing p denotes the element using holes as majority carriers. An element bearing a reference sign + denotes the element having a relatively high impurity concentration, and an element having a reference sign − denotes the element having a relatively low impurity concentration.
Further, on a first principal surface side of a substrate (on the top side of FIG. 1A), the source electrode 8 (the first electrode) is formed. Whereas, on a second principal surface side of the substrate (on the bottom side of FIG. 1A), the drain electrode 9 (the second electrode) is formed. Thus, the first principal surface is the side opposite to the second principal surface.
Further, the n− drift layer 1 (drift layer) is connected to the source electrode 8 (first electrode) via the p base layer 2, the p+ layer 3, and the n+ layer 4. Whereas, the n− drift layer 1 (drift layer) is connected to the drain electrode 9 (second electrode) via the n+ layer 5. Namely, the n− drift layer 1 (drift layer) is formed between the source electrode 8 (first electrode) and the drain electrode 9 (second electrode).
Further, a terminal portion 11 of the device includes the guard ring 10 and the filed plate 13. Still further, as shown in the conventional example of FIGS. 1A and 2, the terminal portion 11 occupies a large area in the periphery of the device. Furthermore, when the breakdown voltage of the device is high, the area occupied by the terminal portion 11 is also large.
In such a conventional example of FIG. 1A, when the device is brought in the ON state according to the voltage of the gate electrode, the n− drift layer 1 becomes conduction, so that an electric current passes from the drain toward the source. Namely, a current flows in a longitudinal direction with respect to the substrate.
Whereas, when the device is brought in the OFF state according to the voltage of the gate electrode, the n− drift layer 1 is depleted due to the expansion of the depletion layer from the junction with the p base layer 2, so that the breakdown voltage is sustained. Whereas, when the voltage between the drain and the source increases, the depletion layer extends along the direction of the thickness D (the longitudinal direction) of the substrate.
Specifically, when the device is brought in the OFF state according to the voltage of the gate electrode 7, and the region between the drain electrode 9 and the source electrode 8 is brought in the reverse bias state, the n− drift layer 1 is depleted due to the expansion of the depletion layer from the junction with the p base layer 2. As a result of this, the breakdown voltage of the device can be sustained.
Then, the electric field intensity of the n− drift layer 1 becomes as shown in the electric field intensity distribution diagram of FIG. 1B at immediately before breakdown. The same diagram indicates that the electric field intensity becomes maximum at the junction site between the p base layer 2 and the n− drift layer 1.
Whereas, with the conventional example of FIG. 1A, generally, the concentration of the n− drift layer 1 is set so that the entire n− drift layer is depleted in the OFF state for the breakdown voltage of the device.
Whereas, in the conventional example of FIG. 1A, for example, a breakdown voltage of 4300 V can be obtained at a concentration of the n− drift layer 1 of about 3×1013/cm3 and a thickness D of 500 μm.
Incidentally, the value of the breakdown voltage of the device of the conventional example of FIG. 1A does not take the width W of the device as a parameter. Further, the value of the breakdown voltage of the device of the conventional example of FIG. 1A depends upon the concentration of the n− drift layer 1 and the thickness D.
Further, when the device is brought in the OFF state according to the voltage of the gate electrode, the guard ring 10 and the field plate 13 arrange the lateral expansion of the depletion layer. Then, the depletion layer does not reach the side.
Specifically, when the device is brought in the OFF state according to the voltage of the gate electrode 7, and a reverse bias is applied between the drain electrode 9 and the source electrode 8, the guard ring 10 and the field plate 13 arrange the lateral expansion of the depletion layer.
Whereas, another conventional semiconductor device includes a multiple parallel pn structures joined alternately and repeatedly in a drift layer, a so-called superjunction structure (see, e.g., JP-A-2000-040822, JP-A-2001-298190, JP-A-2001-244461 and U.S. Pat. No. 6,608,350 (JP-A-2002-217415)).
In such a superjunction structure, the drift layer has a high impurity concentration, and the basic unit of the drift layer is formed with a narrow width.
Further, some semiconductor devices each include a plurality of vertical trenches separated from one another (see, e.g., U.S. Pat. No. 6,608,350 (JP-A-2002-217415)).
However, such a conventional example of FIG. 1A presents a problem of difficulty in reduction in size because of the necessity of a large area for the terminal portion 11. Further, it also presents a problem of a high ON resistance.
Particularly, when the breakdown voltage of the device is high, the area of the terminal portion 11 is large, resulting in a high ON resistance.
For example, the formation of the side of the n− drift layer 1 by dicing results in inferior crystallinity, causing electric field concentration. This results in a reduction of the breakdown voltage. Therefore, a large area is required for the terminal portion 11.
Specifically, when the depletion layer reaches the side of the device, the electric field concentrates thereto, resulting in a reduction of the breakdown voltage. For this reason, the expansion of the depletion layer is restricted to the device surface, thereby to prevent the depletion layer from reaching the side of the device. To this end, a large area is required for the terminal portion 11 in the conventional example of FIG. 1A.
Further, the conventional semiconductor devices of JP-A-2000-040822 and JP-A-2001-298190, and the like have a problem of high cost because of the complicated multiple parallel pn structures.
Whereas, same conventional semiconductor devices may each have multiple parallel pn structures alternately and repeatedly joined in a drift layer, a so-called superjunction structure (see, e.g., U.S. Pat. No. 6,608,350 (JP-A-2002-217415)).
JP-A-2000-040822, JP-A-2001-298190, JP-A-2001-244461 and U.S. Pat. No. 6,608,350 (JP-A-2002-217415) are referred to as related art.